The present invention relates to integrated circuits employing Complementary Metal-Oxide-Semiconductor (CMOS) technology, and more particularly to circuitry for controlling the rate of change of power dissipation of CMOS integrated circuits.
CMOS digital microcircuits are in widespread use today, as a result of their low power consumption requirements. Because of the complimentary nature of the gate circuits employed in CMOS circuits, wherein P-channel and N-channel transistors are connected in parallel and gated by a common gating signal, power is consumed only when the gate switches from one digital state to the other. When the gate is quiescent, either the P or N channel transistor comprising the complimentary gate circuit is nonconductive, so that current may not flow through the gate.
FIG. 1 illustrates a typical CMOS integrated circuit device 10. As is well known, the microcircuits are formed on an integrated circuit die 12, which is mounted on a substrate 14. Electrical connection is made between the microcircuits on the die 12 and the substrate. Such connections can be made in many different ways, for example, by wires 16 which are bonded to terminal pads defined on the die 12 and to terminal pads on the substrate 14. Another common technique is to mount the die on a leadless chip carrier, and the electrical connections are made by contact of pad "bumps" on the die and corresponding "bumps" formed on the surface of the carrier substrate.
The device 10 typically includes a number of input terminals I.sub.O -I.sub.N for receiving input signals, and a plurality of output terminals O.sub.O -O.sub.N at which the device output signals appear. The device 10 receives power from a voltage source V.sub.CC, and may receive clock signals from an external clock. The device 10 may also or alternatively include an internal clock generator for generating clock signals. The clock rate determines the rate at which digital operations are performed by the microcircuits comprising the device 10.
In CMOS digital circuits the power dissipation is a direct function of the number of gates that change state per unit of time, the capacitive loads driven by the gates, and the square of the power supply voltage.
The majority of digital system are synchronous in nature, where fixed clocks sequence operations, and logic activity is instigated on each "tick" of the clocks. In synchronous digital circuits, the number of gates transitioning per unit time depends on the total number of gates in the integrated circuit, the percentage of those gates that change state per clock, and the clock rate. The percentage of gates that change state per clock is determined by the particular program and/or data being processed.
When power is fully applied at turn-on of CMOS circuits, there develops a thermal shock (rapid change of temperature differential) which causes mechanical stress and reduces reliability of the physical and electrical connections between die and substrates. This is also true of subsequent substrate-to-substrate connections in the packaging chain.
Virtually all digital systems have an implicit or explicit reliability goal. On new systems, both the much larger size of integrated circuit (IC) chips and novel packaging schemes (e.g., leadless chip carriers) have caused temperature differentials and thermal shock to become an important factor in reliability. Since most new digital designs use CMOS devices, the invention is widely applicable to help alleviate these problems.
In most cases, power is simply applied "all at once," giving rise to the temperature differential problem. In some cases, this problem could be addressed by controlling the rate of power application by varying the voltage from the power supply. Varying the power supply voltage over time from zero to the final value makes the power supply considerably more complex, and may be impossible for many systems. Furthermore, the digital system cannot operate for a fraction of the warm-up period (during which the voltage is too low.)